1. Technical Field
The present invention relates generally to an improved data processing system and method. More specifically, the present invention provides a system and method for unfolding/replicating logic paths to facilitate propagation delay modeling.
2. Description of Related Art
Logic simulation is often utilized during integrated circuit design in order to simulate the operation of the integrated circuit to perform logic verification. For example, logic simulation may be used to identify the expected operation of the integrated circuit when fabricated, identify potential problems in the integrated circuit design, areas where the integrated circuit design may be optimized, and the like. Typically in logic simulation, when a signal originates from a single source and fans out to multiple sinks (or the same sink following an initial fanout), the value of this signal is uniform for each fanout. That is, every leg out of the source of the signal is considered to be identical thereby resulting in the same signal value. However, this is often not the case in the actual circuit.
Propagation delay because of different wire lengths or combinational gates through which the signal value must traverse, and other factors, all combine to make the propagation rate of a transitioning signal variable for each leg in which the signal fans out. This represents a real problem, especially in asynchronous logic verification. With asynchronous logic, two or more different clock domains are utilized. The asynchronous logic results in variations in propagation delay along different nets of the integrated circuit design. Thus, using a uniform approach to fanouts of logic in an integrated circuit design does not provide an adequate representation of the actual operation of the integrated circuit nets.
In view of the above, it would be beneficial to have a system and method for modeling fanouts of an integrated circuit design such that propagation delay along each net may be modeled.